1. Field of the Invention
The present invention relates to a semiconductor device having co-loaded thereon a semiconductor memory such as a DRAM and a logic circuit, and to a method of manufacturing the semiconductor device.
2. Description of the Related Art
There has in recent years been a rapidly increasing demand for an LSI having co-loaded thereon a large capacity of semiconductor memory and a highly integrated high-speed logic circuit.
For realizing a large capacity of semiconductor memory, a DRAM cell, whose formation process has relatively good consistency with that of the logic circuit and whose unit cell area is relatively small, is suitable. Furthermore, even among such DRAM cells, as the structure whose cell area is small, a so-called “COB type (Capacitor Over Bitline)” memory cell structure, wherein a capacitive element is provided on the bit line, is preferable.
A schematic sectional view of a semiconductor device having this COB type semiconductor memory is illustrated in FIG. 10.
This semiconductor device 101 is constructed having co-loaded a semiconductor memory composed of a memory cell portion 102 and a peripheral circuit portion 103, and a logic circuit 104 on the same semiconductor substrate 110.
This semiconductor memory constitutes a so-called “DRAM (Dynamic Random Access Memory)”.
In a memory cell portion 102, although not illustrated, a number of parallel word lines WL and a number of parallel bit lines BL are disposed in the form of a matrix.
And, over the bit lines (BL) 119, a capacitive element C composed of a memory node electrode (lower electrode) 124, a dielectric film 125, and a plate electrode (upper electrode) 126 is formed to thereby construct the above-described COB type memory cell structure.
The memory node electrode (lower electrode) 124 of the capacitive element C is formed by being separated every memory cell.
The dielectric film 125 and the plate electrode 126 are formed commonly to a plurality of (or all) memory cells.
In the peripheral circuit portion 103 of the semiconductor memory and the logic circuit 104, in order that it may be connected to a diffusion layer 113A formed in a region within a semiconductor substrate 110 that has been separated by an element-isolating layer 112, a contact layer 128 having a laminated structure of two layers, one being a barrier layer (cohered layer) 128A having a laminated structure of, for example, a titanium film and a TiN film and the other being a buried layer 128B consisting of a tungsten film, is formed within a connecting hole passing through laminated insulating films 115, 116, 118, 120, 121, 122, and 127, and a flattening insulating layer 130.
Further, in order that it may be connected to this contact layer 128, a metal wiring layer 131 having a three-layer structure of 131A, 131B, and 131C and constituting an upper-layer wiring is formed on a flattening insulating layer 130.
It is to be noted that, in FIG. 10, a reference symbol 111N denotes an N type well region formed within, for example, a P type semiconductor substrate 110; a reference symbol 111P denotes a P type well region formed within the N type well region 111N; a reference symbol 113B denotes a diffusion layer of the memory cell portion 102; a reference symbol 114 (114A, 114B) denotes a two-layer-structural gate electrode; and a reference numeral 117 denotes a contact portion of the memory node electrode 124 of the capacitive element C.
Also, the portion where the gate electrode 114 is formed over a large-width range corresponds to the portion where the bit line (BL) 119 of the memory cell portion 102 and the peripheral circuit portion 103 are connected to each other.
At this portion, by a plug-shaped contact layer 117′, the bit line (BL) 119 and the gate electrode 114 are connected to each other. A broken line extending leftward from this large-width gate electrode 114 indicates that the word line (WL) of the semiconductor memory that does not exist in this section is extended the position having the same height as that of the gate electrode 114.
The manufacturing process of the semiconductor device 101 is illustrated in FIG. 11 and in FIG. 12.
First, an element-isolating layer 112 is formed in the semiconductor substrate 110 whose region becoming the memory cell portion 102 has formed therein the N type well region 111N and the P type well region 111P. And diffusion layers 113A and 113B are formed in the substrate 110 separated by this element-isolating layer 112.
Next, on the surface of the resulting structure there is formed a thin insulating film (not illustrated) becoming the gate insulating film. Thereafter, the gate electrode 114 having a two-layer structure of 114A and 114B is formed on the surface of the resulting structure. Then, the insulating film (nitride film) 115 is formed over an entire surface of the resulting structure.
This state is illustrated in FIG. 11A. The word line WL indicated by the broken line in the figure is formed at this time.
Next, in such a way as to cover the whole surface of the resulting structure, the layer-insulating layer 116 is formed, after which the thin insulating film 118 is formed on the surface of the resulting structure.
And, on this insulating film 118, the bit line (BL) 119 having a two-layer structure of 119A and 119B is formed, after which the insulating film (nitride film) 120 is formed in such a way as to cover the whole.
Furthermore, in such a way as to cover the whole surface of the resulting structure, the layer-insulating layer 121 is formed.
Thereafter, the connecting holes each passing through the layer-insulating layer 121, insulating film (nitride film) 120, insulating film 118, layer-insulating layer 116, and insulating film (nitride film) 115 are formed in such a way as to reach the diffusion layer 113B. And within each of these connecting holes, for example, a polycrystalline silicon layer is formed as the contact layer 117 of the memory node electrode.
Furthermore, after flattening of the surface of the resulting structure, as illustrated in FIG. 11B, the insulating film (nitride film) 122 is formed in such a way as to cover the whole surface of the resulting structure whose upper surface has been flattened. This insulating film (nitride film) 122 becomes a stopper for later etching.
Next, in the memory cell portion 102, in the insulating film (nitride film) 122 and the layer-insulating layer 121 located under this insulating film 122, an opening corresponding to each memory cell is formed by etching so as to reach the contact layer 117.
And, the memory node electrode (lower electrode) 124 is formed in such a way as to bed in this opening and extend upper than the same.
The formation of this memory node electrode 124 can be performed, for example, as follows.
An oxide film (not illustrated) becoming a sacrifice film is deposited on the resulting surface. The groove having a pattern defining the memory node electrode (lower electrode) 124 is formed up to the depth until which the groove passes through the oxide film and insulating film (nitride film) 122 and further is connected to the contact layer 117 within the layer-insulating layer 121 located under the film 122.
And, in such a way as to bed in this groove, the material of the memory node electrode 124 is deposited therein and, in such a way as for this material to remain on the side walls and the bottom of the groove, the memory node electrode 124 is formed.
In such a way as to cover the memory node electrode (lower electrode) 124, the dielectric film 125 and the plate electrode (upper electrode) 126 are formed over an entire surface of the memory cell portion 102 to thereby construct the capacitive element C.
And, as illustrated in FIG. 12, in such a way as to cover this capacitive element C, the layer-insulating layer 127 is formed wholly thereover.
Next, in order to flatten the level difference between the respective portions of the resulting structure of the memory cell portion 102, the flattening insulating layer 130 is deposited to thereby flatten the surface of the resulting structure.
Thereafter, the connecting holes passing from the flattening insulating layer 130 through the insulating films 127, 122, 120, 118, 116, and 115 located thereunder are formed to thereby form in each of these connecting holes the contact layer 128 consisting of the buried metal layer.
However, in this COB type memory cell structure, in order to make the memory have a sufficiently large capacity, it is needed to increase the height of the capacitive element C. For example, even with the use of a 0.25 μm rule, the height reaches a value as great as approximately 1 μm.
As a result of this, in a case of having flattened the level difference that occurs in the memory cell portion 102, the depth of the contact layer 128 in the peripheral circuit portion 103 and the logic circuit 104 becomes approximately as great as 2 μm. Therefore, in a case where micronization proceeds from now onwards, it is estimated that it will become more and more difficult to make a high integration of the peripheral circuit portion 103 and the logic circuit 104.
Also, the flattening step of flattening the level difference occurring due to the capacitive element C becomes further complex due to the progress of the micronization.
When the aspect ratio of the connecting hole becomes high in the construction of FIG. 10, concretely saying, for example, it becomes difficult to form the TiN film used for the barrier layer 128A of the contact layer 128.
On the other hand, it is also considered to adopt the manufacturing method of forming wiring for use in the peripheral circuit portion 103 and logic circuit 104 while preferentially forming the connecting holes, with the level difference occurring due to the capacitive element C of the memory cell portion 102 remaining the same without being flattened. However, in this case, the existence of the level difference becomes an obstacle to forming the metal wiring layer 131 serving as an upper-layer wiring. Therefore, in this case, also, it becomes difficult to make a higher integration of such portions 103 and 104.
Also, studies have now been also made of the method of decreasing the height of the capacitive element C needed to ensure a desired magnitude of capacity, by using a high-dielectric-constant material in order to form the dielectric film 125 of the capacitive element C.
However, in the case of a high-dielectric-constant material as presently proposed, although the dielectric constant is high, difficulties are encountered in making the dielectric film have a decreased thickness of on the order of several nm to ten and odd nm. Therefore, it is difficult to apply this material to the micronized capacitive element C.
Accordingly, in order to accomplish the increase in the capacity, it results that the height of the capacitive element C becomes greater, with the result that the consistency thereof with the increase in the degree of integration of the logic circuit becomes lost.